A NAND flash memory which includes a plurality of memory cells stacked in three dimensions is known as a type of a nonvolatile memory.
The NAND flash memory is configured such that the plurality of memory cells are connected to one bit line. Therefore, a read failure may be caused by an influence of some memory cells among the plurality of connected memory cells. The NAND flash memory reduces such a readout failure by using an ECC circuit. In the ECC circuit, an LDPC (Low-Density Parity Check) technique is employed in which an error correction capability is extremely high. In the LDPC correction, an LLR (log likelihood ratio) value used in decoding is dynamically changed between “0” and “1” and, a probability distribution thereof is used. Therefore, data having an accurate probability distribution can be corrected with high performance.
The LDPC technique has an extremely high error correction capability. On the other hand, the correction performance is significantly reduced by a hard bit error (HBE) which causes a large deviation in the probability distribution used in the LDPC technique. Therefore, there is a need to establish a system that accounts for the HBE.